1. Field of the Invention
This invention relates to a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET), and more particularly, to a manufacturing method of multi-layered gate electrode on a MOSFET.
2. Description of Related Art
As semiconductor devices are highly integrated, the gate electrode of a MOSFET becomes narrower. If the gate electrode is decreased in width, its electric resistance is increased, thereby lowering the operating speed of the semiconductor device.
A phosphorus-doped polysilicon layer is formed as a gate electrode with an aim of reducing the resistance of the gate electrode. The phosphorous atoms in the polysilicon layer are doped to lower the resistance of the gate electrode. The phosphorus-doped polysilicon layer is formed in a process comprising an annealing step for uniformly distributing the phosphorus atoms in it. For achieving the distribution, the annealing step should be performed at a high temperature. However, in this high temperature annealing, the phosphorus atoms often accumulate in a great numbers near the interface between the polysilicon layer and the gate dielectric located beneath the polysilicon layer. Since the thickness of the gate dielectric is desirably reduced, some of the accumulated phosphorus atoms can penetrate through the gate dielectric layer to the channel region beneath the gate dielectric, thereby undesirably lowering the gate breakdown voltage.
A phosphorus-doped amorphous silicon layer is proposed for use in gate formation to reduce the accumulation phenomenon of the phosphorus atoms. However, the phosphorus atoms do not distribute uniformly to satisfy requirements, and thereby cause an undesirable raise in the gate resistance.